Habilitation Defense: Matthias Függer

Matthias Függer

Abstract: The design and analysis of low-level computing devices directly implemented in hardware is commonly based on finite state machine models. In this work we review some of the assumptions made in these designs and discuss techniques for the cases where the assumptions fail to hold. The work concentrates on three such aspects:

  • computing under conditions where low-level timing effects cannot be neglected,
  • when non-binary signals play a central role, and
  • computing within a changing infrastructure, i.e., dynamic networks.

While most of this work is devoted to implementations in silicon, microbiological circuits are discussed in the outlook.


  • Miloš KRSTIĆ (Rapporteur), University Potsdam, IHP, Germany
  • Yoram MOSES (Rapporteur), Technion, Israel
  • Alex YAKOVLEV (Rapporteur), Newcastle University, GB
  • Stefan HAAR (Examinateur), INRIA, LMF, ENS Paris-Saclay, Université Paris-Saclay, France
  • Maria POTOP-BUTUCARU (Examinatrice), Sorbonne Université, LIP6, France